The present invention is related to semiconductor memories, especially dynamic random access memory (DRAM). In particular, the present invention relates to a method and apparatus of handling refresh operations in a semiconductor memory such that the refresh operations do not interfere with external access operations.
A conventional DRAM memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM cell, which consists of 4 to 6 transistors. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each refresh operation of a DRAM cell consumes memory bandwidth. It is possible for an external access to be initiated at the same time that a refresh access is required. In this case, the external access must be delayed until after the refresh access has been performed. In general, this prevents DRAM cells from being operated as SRAM cells, because SRAM cells do not require refresh operations.
Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device has required an external signal to control refresh operations. (See, 131, 072-Word by 8-Bit CMOS Pseudo Static RAM, Toshiba Integrated Circuit Technical Data (1996).) Moreover, external accesses to this DRAM device are delayed during the memory refresh operations. As a result, the refresh operations are not transparent and the resulting DRAM device cannot be fully compatible with an SRAM device.
In another prior art scheme, a high-speed SRAM cache is used with a relatively slow DRAM array to speed up the average access time of the memory device. (See, U.S. Pat. No. 5,559,750 by Katsumi Dosaka et al, and xe2x80x9cData Sheet of 16 Mbit Enhanced SDRAM Family 4Mxc3x974, 2Mxc3x978, 1Mxc3x9716xe2x80x9d by Enhanced Memory Systems Inc., 1997.) The actual access time of the device varies depending on the cache hit rate. Circuitry is provided to refresh the DRAM cells. However, the refresh operation is not transparent to external accesses. That is, the refresh operations affect the memory access time. Consequently, the device cannot meet the requirement of total deterministic random access time.
Other prior art schemes use multi-banking to reduce the average access time of a DRAM device. Examples of multi-banking schemes are described in xe2x80x9cData sheet, MD904 To MD920, Multi-bank DRAM (MDRAM) 128Kxc3x9732 to 656Kxc3x9732xe2x80x9d by MoSys Inc., 1996, and in xe2x80x9cAn Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM""sxe2x80x9d by Kazushige Ayukawa et al, IEEE JSSC, vol. 33, No. May 5, 1998, pp. 800-806. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle. Another prior art scheme uses a read buffer and a write buffer to take advantage of the sequential or burst nature of an external access. An example of such a prior art scheme is described in U.S. Pat. No. 5,659,515, entitled xe2x80x9cSemiconductor Memory Device Capable of Refresh Operation in Burst Modexe2x80x9d by R. Matsuo and T. Wada. In this scheme, a burst access allows a register to handle the sequential accesses of a transaction while the memory array is being refreshed. However, this scheme does not allow consecutive random accesses. For example, the memory cannot handle a random access per clock cycle.
Another prior art scheme that attempts to completely hide refresh operations in a DRAM cell includes the scheme described in U.S. Pat. No. 5,642,320, entitled xe2x80x9cSelf-Refreshable Dual Port Dynamic CAM Cell and Dynamic CAM Cell Array Refreshing Circuitxe2x80x9d, by H. S. Jang. In this scheme, a second port is added to each of the dynamic memory cells so that refresh can be performed at one port while a normal access is carried out at the other port. The added port essentially doubles the access bandwidth of the memory cell, but at the expense of additional silicon area.
Another prior art scheme that attempts to completely hide the refresh operations in an asynchronous DRAM is described in U.S. Pat. No. 4,549,284, entitled xe2x80x9cDynamic MOS Random Access Memoryxe2x80x9d, by Kunihiko Ikuzaki. In this scheme, an automatic refresh circuit is incorporated in an asynchronous DRAM to generate a refresh cycle after an external access cycle is performed. In the absence of an external access, an internal oscillator continues to generate refresh cycles. Thus, the memory device is constantly performing refresh operations, thereby wasting power.
Moreover, the oscillation period of the oscillator is set by the transconductance of an MOS transistor and a capacitor, which varies with process and temperature. Within a typical process and commercial temperature range, the oscillation period varies by up to a factor of two. As a result, it becomes difficult to synchronize the external accesses and the refresh operations. For this reason, the memory device is not suitable for high-speed operations in the auto-refresh mode.
Accordingly, it would be desirable to have a DRAM device that handles refresh operations in a manner that is completely transparent to an external accessing memory client for both low-speed and high-speed operations. It would further be desirable if such a DRAM device only performed refresh operations at the times when the memory cells need to be refreshed (i.e., at a rate determined mainly by the charge leakage mechanism of the memory cells, and not by the circuit operation of the automatic refresh circuit).
Accordingly, the present embodiment provides a memory device (or an embedded memory block) that includes a plurality of memory cells, which must be periodically refreshed in order to retain data values. In one embodiment, the memory cells are DRAM cells arranged in an array having a plurality rows and columns. In a particular embodiment, the array is divided into a plurality of banks.
The memory device includes a plurality of terminals for receiving signals from an external accessing client. These signals can include a clock signal, an address signal, a write/read indicator signal, and address strobe signal and a reset signal. However, these signals do not include a signal that indicates that a refresh operation must be performed.
To implement refresh operations, the memory device includes a refresh controller that periodically asserts a refresh request signal, which is used to indicate that a refresh operation is pending. The refresh controller also provides a refresh address identifying one of the rows of the array. The refresh controller increments the refresh address each time that the refresh request signal is asserted.
The memory device also includes a memory array sequencer for controlling the timing of external accesses and refresh accesses within the memory device. In general, the memory array sequencer ensures that the required refresh accesses are performed without interfering with any external accesses.
More specifically, the memory array sequencer synchronizes external accesses and refresh accesses with different edges of an external clock signal. In one embodiment, external accesses are synchronized (initiated) in response to rising edges of the external clock signal. The external accesses are then completed during the first half cycle of the clock period (e.g., while the clock signal has a high state). In this embodiment, pending refresh accesses are synchronized (initiated) in response to falling edges of the external clock signal. The refresh accesses are then completed during the second half cycle of the clock period (e.g., while the clock signal has a low state).
In another embodiment, external accesses are synchronized (initiated) in response to rising edges of the external clock signal. The external accesses are performed as quickly as possible. Pending refresh accesses are then synchronized (initiated) in response to the end of the external accesses. The refresh accesses are completed prior to the next rising edge of the external clock signal. This embodiment allows the external accesses and refresh accesses to be performed as quickly as possible, without being dependent on the duty cycle of the external clock signal.
In yet another embodiment, a clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles. In this embodiment, the memory system can include a memory array sequencer configured to enable N external accesses and one refresh access to be consecutively performed during N cycles of the clock signal, wherein N is an integer equal to two or more. This memory system can include a clock divider circuit configured to provide a divided clock signal that is activated for one period of every N periods of the clock signal, and means for initiating the refresh access only when the divided clock signal is activated.
A corresponding method includes the steps of operating the memory system in response to a clock signal, and enabling N external accesses and one refresh access to be consecutively performed during N cycles of the clock signal, wherein N is an integer equal to two or more. In one embodiment, the clock signal is divided to create a divided clock signal that is activated for one period of every N periods of the clock signal, and a refresh access only enabled when the divided clock signal is activated.
The refresh access can be performed at the beginning of the N cycle period. Alternately, the refresh access can be performed only during the second half of one of the N cycles of the clock signal. In another variation, each of the N external accesses is initiated only during a first half of a corresponding one of the N cycles. In another variation, the refresh access is initiated in response to an end of a first one of the N external accesses, and a second one of the N external accesses is initiated in response to an end of the refresh access.